Memory Efficient Scalable Decoder Architectures for Low Density Parity Check Codes

We present a memory efficient low density parity check (LDPC) decoder that implements a modified Sum Product Algorithm (SPA). A memory efficient implementation for the Min-Sum algorithm is also presented. Serial and scalable partly parallel architectures with both parallel flooding schedule and serial message passing schedule are presented for the regular SPA, modified SPA and Min-Sum algorithms. Compared to a regular SPA decoder the proposed modified SPA architecture reduces the number of extrinsic messages stored at the decoder that forms the bulk of the hardware. Memory reduction increases with the rate of the code and up to 75% savings is achieved for a rate 9/10 code. The architecture for serial scheduling has a faster convergence over parallel scheduling and can save up to 40% decoding time for 20 decoding iterations. Simulation results show that the proposed changes to the SPA do not degrade the bit error rate (BER) performance and convergence of the decoder. The proposed architecture is scalable in logic for achieving various throughput and latency requirements by scaling the computational units of a serial architecture and partitioning the memory for parallel read and write access.